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| White Electronic Designs WV3HG264M72EER-D7 ADVANCED* 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM FEATURES 244-pin, dual in-line memory module (Mini-DIMM) Fast data transfer rates: PC2-6400*, PCS-5300*, PC2-4200 and PC2-3200 Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM components VCC = VCCQ = 1.8V 0.1V VCCSPD = 1.7V to 3.6V Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Programmable CAS# latency (CL): 3, 4, 5 and 6 On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM JEDEC Standard 1.8V I/O (SSTL_18 Compatible) Gold (Au) edge contacts Dual Rank RoHS compliant Package option * 244 Pin Mini-DIMM * PCB - 30.00mm (1.181") TYP DESCRIPTION The WV3HG264M72EER is a 2x64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of eighteen 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 244-pin DIMM FR4 substrate. * This product is under development, is not qualified or characterized and is subject to change without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option OPERATING FREQUENCIES PC2-3200 Clock Speed CL-tRCD-tRP *Consult factory for availability. PC2-4200 266MHz 4-4-4 PC2-5300* 333MHz 5-5-5 PC2-6400* 400MHz 6-6-6 200MHz 3-3-3 August 2006 Rev. 3 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS NC VCCQ CKE0 VCC NC NC VCCQ A11 A7 VCC A5 Pin No. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 Symbol A4 VCCQ A2 VCC VSS VSS NC VCC A10/AP BA0 VCC WE# VCCQ CAS# VCCQ CS1# ODT1 VCCQ NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SA0 SA1 Pin No. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 Symbol VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC VCCQ CKE1 VCC NC NC VCCQ A12 A9 VCC A8 A6 Pin No. 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 Symbol VCCQ A3 A1 VCC CK0 CK0# VCC A0 BA1 VCC RAS# VCCQ CS0# VCCQ ODT0 A13 VCC NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS SDA SCL VCCSPD WV3HG264M72EER-D7 ADVANCED PIN NAMES Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0, ODT1 CK0,CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# RESET# DM (0-8) VCCSPD VCC VCCQ VSS SA0-SA2 SDA SCL NC VREF Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination control Clock Inputs Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable Register Reset Input Data Masks SPD Power Voltage Supply (1.8V0.1V) I/O Power (1.8V) Ground SPD address SPD Data Input/Output Serial Presence Detect(SPD) Clock Input Spare pins, No connect Input/Output Reference RESET (pin 18) is connected to both OE of the PLL and Reset# of the register . August 2006 Rev. 3 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-D7 ADVANCED FUNCTIONAL BLOCK DIAGRAM RCS1# RCS0# DQS0 DQS0# DM0 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQS4 DQS4# DM4 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1# DM1 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQS5 DQS5# DM5 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DQS2# DM2 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQS6 DQS6# DM6 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DQS3# DM3 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQS7 DQS7# DM7 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS8 DQS8# DM8 DM/ RDQS CS# DQS DQS# DM/ RDQS CS# DQS DQS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VCCSPD Serial PD SCL WP A0 A1 A2 SDA VREF VSS SA0 SA1 SA2 VCC/VCCQ Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs CS0# CS1# BA0-BA1 A0-A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET#** CK#** CK** 1:2 R E G I S T E R RST# RCS0# -> CS# : DDR2 SDRAMs RCS1 -> CS# : DDR2 SDRAMs RBA0 - RBA1 -> BA0-BA1 : DDR2 SDRAMs RA0-RA13 -> A0-A13 : DDR2 SDRAMs RRAS# -> RAS# DDR2 SDRAMs RCAS# -> CAS# DDR2 SDRAMs RWE# -> WE# : DDR2 SDRAMs RCKE0 -> CKE : DDR2 SDRAMs RCKE1 -> CKE : DDR2 SDRAMs RODT0 -> ODT : DDR2 SDRAMs RODT1 -> ODT : DDR2 SDRAMs CK0 CK0# RESET# OE P L L PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs PCK0# -> PCK6#, PCK8#, PCK9# -> CK# : DDR2 SDRAMs PCK7 -> CK : Register PCK7 -> CK# : Register ** RESET#, CK AND CK# connects to both Registers. Other signals connct to one of two Registers. NOTE: All resistor values are 22 ohms 5% unless otherwise specified. August 2006 Rev. 3 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage VCCL Supply voltage I/O Reference voltage I/O Termination voltage Symbol VCC VCCQ VCCL VREF VTT Min 1 .7 1 .7 1 .7 0.49 x VCCQ VREF-0.04 Typical 1 .8 1 .8 1 .8 0.50 x VCCQ VREF WV3HG264M72EER-D7 ADVANCED Max 1 .9 1 .9 1 .9 0.51 x VCCQ VREF + 0.04 Unit V V V V V Notes 1 4 4 2 3 Notes: 1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC; VCCL track with VCC. ABSOLUTE MAXIMUM RATINGS Symbol VCC VCCQ VCCL VIN, VOUT TSTG TCASE Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on VCCL pin relative to VSS Voltage on any pin relative to VSS Storage temperature Device operating temperature Input leakage current; Any input 0V IOZ IVREF INPUT/OUTPUT CAPACITANCE TA=25 0 C, f=1 00MHz Parameter Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#) Input capacitance ( CKE0, CKE1), (ODT0, ODT1) Input capacitance (CS0#, CS1#) Input capacitance (CK0, CK0#) Input capacitance (DM0 - DM8), (DQS0 - DQS8) Input capacitance (DQ0 - DQ63), (CB0 - CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (E6) CIN5 (E5) COUT1 (E6) COUT1 (E5) Min 9 9 9 10 9 9 9 9 Max 11 11 11 11 11 12 11 12 Unit pF pF pF pF pF pF pF pF August 2006 Rev. 3 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Parameter Operating temperature Symbol TOPER Rating 0C to 85C WV3HG264M72EER-D7 ADVANCED OPERATING TEMPERATURE CONDITION Units C Notes 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51 .2 2. At 0 - 85C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Input High (Logic 1 ) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VCCQ + 0.300 VREF - 0.125 Unit V V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter AC Input High (Logic 1 ) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 1 ) Voltage DDR2-667 AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 AC Input Low (Logic 1 ) Voltage DDR2-667, DDR2-800(TBD) Symbol VIH(AC) VIH(AC) VIL(AC) VIL(AC) Min VREF + 0.250 VREF + 0.200 -- -- Max -- -- VREF - 0.250 VREF - 0.200 Unit V V V V August 2006 Rev. 3 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-D7 ADVANCED DDR2 ICC SPECIFICATIONS AND CONDITIONS Includes DDR2 SDRAM components only; TA = 0C, VCC = 1.9V Symbol Parameter Operating one bank ICC0* activeprecharge; Operating one bank ICC1* activereadprecharge; Precharge powerICC2P** down current; Precharge quite ICC2Q** standby current; Precharge ICC2N** standby current; ICC3P** Active powerdown current; Active standby current; Operating burst write current; Operating burst read current; Burst auto refresh current; Self refresh current; Operating bank interleave read current; Condition tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 806 TBD 665 1337 534 1292 403 1292 Unit mA IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data pattern is same as ICC4W. TBD 1472 1427 1427 mA All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 644 644 644 mA All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; tCK = tCK(ICC), CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal TBD 1130 1040 1040 mA TBD 1220 1040 716 1490 1130 1040 716 1400 1130 1040 716 1400 mA mA mA mA TBD TBD ICC3N** TBD ICC4W* TBD 1832 1652 1562 mA ICC4R* TBD 1877 1697 1562 mA ICC5** TBD 3200 3020 3020 mA ICC6** TBD 144 144 144 mA ICC7* All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(ICC) - 1*tCK(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING TBD 2552 2552 2552 mA Notes: ICC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition. August 2006 Rev. 3 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC TIMING PARAMETERS WV3HG264M72EER-D7 ADVANCED 0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V Parameter CL=6 Clock cycle time Clock CL=5 CL=4 CL=3 CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS Data DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Data Strobe DQS-DQ skew, DOS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Symbol tCK(6) tCK(5) tCK(4) tCK(3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS 806 Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 665 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 534 Max 8000 8000 8000 0.55 0.55 Min 3,750 5,000 0.45 0.45 MIN (tCH, tCL) 125 +450 -125 -500 125 +500 tAC(MAX) 100 225 0.35 340 400 tHP - tQHS tQH - tDQSQ 0.35 0.35 +400 -450 0.2 0.2 240 300 0.9 0.4 0 0.35 0.6 0.4 0.6 1.1 0.6 0.9 0.4 0 0.35 0.4 +450 150 275 0.35 Max 8,000 8,000 0.55 0.55 Min - 403 Max 8,000 8,000 0.55 0.55 Min 3000 3750 5000 0.45 0.45 MIN(tCH, tCL) -125 -450 Unit ps ps ps tCK tCK ps 5,000 5,000 0.45 0.45 MIN (tCH, tCL) -125 -600 125 +600 tAC(MAX) ps ps ps ps tAC(MAX) 100 175 0.35 tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tCK 450 ps ps ns tCK tCK +500 ps tCK tCK 350 1.1 0.6 ps tCK tCK ps tCK 0.6 tCK tCK tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.9 0.4 0 0.35 0.4 1.1 0.6 WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25 AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. August 2006 Rev. 3 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-D7 ADVANCED AC TIMING PARAMETERS (continued) 0C TCASE < +85C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V Parameter Address and control input pulse width for each input Address and control input setup time Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK, CK# uncertainty REFRESH to Active or Refresh to Refresh command interval Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off ODT Symbol tIPW tIS tIH tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tlSXR tAOND tACN tAOFD tAOF 806 Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 665 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 534 Max 403 Min 0.6 200 275 2 55 7.5 15 37.5 40 7.5 15 tWR + tRP 7.5 15 tRP + tCK 2 tIS+tCK+tIH 105 TBD TBD ODT turn-on (power-down mode) tAONPD TBD TBD ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any non-READ command CKE minimum high/low time tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE TBD TBD Min Max Min Max 0.6 0.6 250 350 375 475 2 2 55 55 7.5 7.5 15 15 37.5 37.5 37.5 37.5 37.5 70,000 40 70,000 40 70,000 7.5 7.5 15 15 tWR + tRP tWR + tRP 7.5 10 15 15 tRP + tCK tRP + tCK 2 2 tIS+tCK+tIH tIS+tCK+tIH 70,000 105 70,000 105 70,000 7.8 7.8 7.8 tRFC(MIN) tRFC(MIN) tRFC(MIN) + 10 + 10 + 10 200 200 200 tIS tIS tIS 2 2 2 2 2 2 tAC(MAX) tAC(MAX) tAC(MAX) tAC(MIN) tAC(MIN) tAC(MIN) + 1000 + 1000 + 1000 2.5 2.5 2.5 2.5 2.5 2.5 tAC(MAX) tAC(MAX) tAC(MAX) + tAC(MIN) + tAC(MIN) + tAC(MIN) 600 600 600 2 x tCK + 2 x tCK + 2 x tCK + tAC(MIN) + tAC(MIN) + tAC(MIN) + tAC(MAX) tAC(MAX) tAC(MAX) 2000 2000 2000 + 1000 + 1000 + 1000 2.5 x tCK + 2.5 x tCK + 2.5 x tCK + tAC(MIN) + tAC(MIN) + tAC(MIN) + tAC(MAX) tAC(MAX) tAC(MAX) 2000 2000 2000 +1000 +1000 + 1000 Unit tCK ps ps ps ns ns ns ns ns ns ns ns ns ns ns tCK ns ns ns ns tCK ps tCK ps tCK ps Self Refresh Command and Address ps ps tCK tCK tCK tCK tCK tCK TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 3 8 2 7-AL 2 3 3 8 2 6-AL 2 3 3 8 2 6-AL 2 3 AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. August 2006 Rev. 3 Power-Down 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-D7 ADVANCED ORDERING INFORMATION FOR D7 Part Number WV3HG264M72EER806D7xG** WV3HG264M72EER665D7xG** WV3HG264M72EER534D7xG WV3HG264M72EER403D7xG Clock Speed/ Data Rate 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP ** Contact factory for availability. NOTES: * RoHS product. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case"x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR D7 FRONT VIEW 82.15 (3.234) 81.15 (3.222) 3.80 (0.150) MAX 4.10 (0.161) (2X) 3.90 (0.154) 2.10 (0.083) (2X) 1.90 (0.075) 1.80 (0.071) D X2 6.0 (0.236) TYP 1.0 (0.039) TYP 2.0 (0.079) TYP 0.60 (0.024) TYP 0.50 (0.020) R 30.00 (1.181) 20.0 (0.787) TYP 10.0 (0.394) TYP 1.10 (0.043) 0.90 (0.035 ) PIN 1 42.90 (1.689) TYP PIN 122 78.0 (3.071) TYP 3.6 (0.142) TYP BACK VIEW 3.800.10 (0.1500.004) (1.30) 0.051 1.000.05 (0.0390.002) 0.25 MAX (0.010) 3.3 (0.130) TYP PIN 244 33.6 (1.323) TYP Detail A 3.6 (0.142) TYP 38.4 (1.512) TYP Detail B 0.60 TYP 0.024 TYP 0.450.03 MAX (0.0180.001) PIN 123 3.2 (0.126) TYP * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) August 2006 Rev. 3 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG264M72EER-D7 ADVANCED PART NUMBERING GUIDE WV 3 H G 2 64M 72 E E R xxx D7 x G WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH (x8) 1.8V REGISTERED SPEED (Mb/s) PACKAGE 244 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT August 2006 Rev. 3 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title WV3HG264M72EER-D7 ADVANCED 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM Revision History Rev # Rev 0 Rev 1 Rev 2 Rev 3 History Created 1.1 Changed IDD to ICC 2.0 Added 800Mb/s as TBD 3.0 Updated maximum ratings spec 3.1 Updated AC timing specs Release Date September 2005 December 2005 February 2006 August 2006 Status Advanced Advanced Advanced Advanced August 2006 Rev. 3 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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